November 24, 2020

The speed and complexity of the latest TLC and QLC flash technologies set new challenges in designing large capacity high performance SSD devices, from the hardware (signal integrity, power management) and the firmware (flash algorithms, error correction) point of view. Massive amounts of accurate data must be collected and analyzed to characterize the flash endurance, errors, defects, operation’s timing and power.
NanoCycler HS, bundled with BarnieMAT data analytics, provides the best-in-class and most cost effective solution for the exploration of the NAND memories.

NanoCycler HS:

Supports endurance and functional testing of NAND devices by providing C++ and Python API with full ONFI command set and with customizable signal sequences.

Exercises and stresses at-speed – up to 1.6 GT/sec – the devices under test faithfully replicating the use conditions of the application.

Provides high-accuracy – 10 mV precision – programmable power supplies for accurate voltage margins analysis.

Captures the power consumption for each supply at 50 nsec sampling rate with 1 mA resolution. Flash operations power consumption data are processed in real time to provide high resolution current consumption traces, and key metrics (peak, average, distributions) over long period of time.

Characterizes the flash interface timing with 1 nsec I/O edge placement and 20 nsec flash response time acquisition.

Has a scalable and expandable architecture, from 1 to 48 test sites, to optimize cost and long term investment.

Allows full independence of the test sites where each device under test can run at individual temperature, timing, voltage levels, with different test programs.

Integrates the data analysis environment to post-process and present the results to accelerate time to product.

Highest quality characterization results at the lowest cost and effort – NanoCycler HS represents a future-safe investment to design high-performance reliable mass storage devices.



March 5, 2019

NplusT took part in the TETRAMAX poster session held at the 2020 edition of HiPEAC, the main European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems, attracting over 500 delegates each year.

The poster session showcased the projects funded in the framework of the European “Smart Anything Everywhere (SAE)” initiative, in the domain of customized low energy computing (CLEC) for CPS and the IoT, including the “HS-CHAR: High Speed Characterization of Mass Storage Devices” technology transfer project carried out by NplusT and PCB Design and devilered in December 2019.

The results of the “HSCHAR” project contributed to upgrade NplusT’s technology for NAND characterization, paving the way for the forthcoming release of NanoCycler High Speed, the best-in-class and most cost effective solution for the exploration of the NAND memories.


Legal Office

Loc. Castelfranco 132
05026 Montecastrilli
Terni, Italy

+39 075 5714845

info@n-plus-t.com

Laboratories

Via Donatella 12
06132 San Martino in Campo
Perugia, Italy

Capitale Sociale (Paid-up Capital) € 121.000,00 I.V.
Cod. Fisc. / Partita IVA (Vat Number) 00702760554
Sede CCIAA / n. REA : TR / 69772, PG / 272888
Iscriz. Reg. Imprese TR n. 00702760554


Privacy