NplusT has achieved a major milestone with the granting of its second patent, further strengthening its intellectual property portfolio in cutting-edge testing solutions for electronic devices. This latest patent safeguards the company’s fast, multi-range, low-leakage current sensing circuitry, a critical technology for precise and efficient device evaluation, already applied in specific TESTMESH configurations.
Building on this momentum, NplusT is also advancing its third patent, currently pending approval. This innovation introduces a structured test system architecture, designed to interface seamlessly with electronic memory devices, optimizing the testing of matrix-arranged memory cells—particularly for emerging neuromorphic memory technologies. Such technology is the core of the TESTMESH TMC-100 equipment.
“These achievements reaffirm our commitment to technological excellence and continuous innovation.” said Tamas Kerekes, President and CEO of NplusT. “They further establish our company as a leading provider of non-volatile memory testing solutions, enabling the next generation of advanced memory devices.”
With a growing portfolio of proprietary technologies, NplusT continues to push the boundaries of non-volatile memory testing, delivering solutions that enhance speed, accuracy, and reliability in the rapidly evolving semiconductor landscape.
