research – NplusT

NplusT has achieved a major milestone with the granting of its second patent, further strengthening its intellectual property portfolio in cutting-edge testing solutions for electronic devices. This latest patent safeguards the company’s fast, multi-range, low-leakage current sensing circuitry, a critical technology for precise and efficient device evaluation, already applied in specific TESTMESH configurations.

Building on this momentum, NplusT is also advancing its third patent, currently pending approval. This innovation introduces a structured test system architecture, designed to interface seamlessly with electronic memory devices, optimizing the testing of matrix-arranged memory cells—particularly for emerging neuromorphic memory technologies. Such technology is the core of the TESTMESH TMC-100 equipment.

“These achievements reaffirm our commitment to technological excellence and continuous innovation.” said Tamas Kerekes, President and CEO of NplusT. “They further establish our company as a leading provider of non-volatile memory testing solutions, enabling the next generation of advanced memory devices.”

With a growing portfolio of proprietary technologies, NplusT continues to push the boundaries of non-volatile memory testing, delivering solutions that enhance speed, accuracy, and reliability in the rapidly evolving semiconductor landscape.

NplusT’s technology was recently featured in a research publication and played a critical role in enabling precise data collection and testing. Using NanoCycler as core tool for acquiring real-device data during the entire NAND life cycle, Luo Zheng’s dissertation, titled “Research and Development of Efficient Testing Technology for Ultra-large Capacity 3D Flash Memory”, delves into enhancing the reliability and lifespan of 3D NAND flash memory.

Written under the guidance of Prof. Han Guojun at the Department of Electronic Information, Guangdong University of Technology, in Guangzhou, China, the research focuses on developing machine learning models to accurately predict flash memory lifespan. The work aims to optimize storage system performance by reducing the impact of noise on lifespan prediction accuracy.

The NplusT team extends their congratulations to Luo Zheng for earning the degree of Master of Electronic Information.

Tamas Kerekes, CEO and President of Nplust, was a speaker in the recent seminar held on December 14th at the Faculty of Computer Science of the University of Ferrara, alongside prominent names from the Storage industry and research. The presentation, titled “Make the NAND Work” is available at this link.

Nplust’s CTO Nicola Campanelli was a speaker at the recent Italian Mathematical Union conference Cryptography and Coding, held at University of Perugia’s Mathematics and Computer Science Department on September 21-22, 2023.

The presentation, titled “The Coding Theory in Flash Memory Applications” highlighted the theory’s importance in error correction, data degradation detection, and data loss prevention strategies when using high performance NAND memories. The presentation is available at this link.

NplusT Secures Second Patent, Advances Third Innovation

NanoCycler Powers Research in 3D Flash Memory Lifespan Prediction: Luo Zheng Earns Master’s Degree at Guangdong University of Technology

NplusT at the University of Ferrara Storage Seminar

NplusT at the Cryptography and Coding Conference – University of Perugia

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